? 1/8 ESDA6V1P6 quad transil? array for esd protection rev. 2 sot-666ip (internal pad) may 2004 main applications where transient overvoltage protection in esd sensitive equipment is required, such as : computers printers communication systems and cellular phones video equipment this device is particularly adapted to the protection of symmetrical signals. features 4 unidirectional transil? functions breakdown voltage v br = 6.1 v min. low leakage current < 500 na very small pcb area < 2.6 mm 2 description the ESDA6V1P6 is a monolithic array designed to protect up to 4 lines against esd transients. the device is ideal for situations where board space saving is required. benefits high esd protection level high integration suitable for high density boards complies with the following standards: iec61000-4-2 level4: 15kv (air discharge) 8kv (contact discharge) mil std 883e-method 3015-7: class3 25kv hbm (human body model) order codes part number marking ESDA6V1P6 b asd? functional diagram i/o1 i/o2 gnd i/o4 i/o3
ESDA6V1P6 2/8 ? absolute maximum rating (t amb = 25c) thermal resistances electrical characteristics (t amb = 25c) symbol parameter value unit v pp esd discharge iec61000-4-2 air discharge iec61000-4-2 contact discharge 15 8 kv p pp peak pulse power (8/20s) (see note 1) t j initial = t amb 100 w t j junction temperature 125 c t stg storage temperature range -55 to +150 c t l maximum lead temperature for soldering during 10 s at 5mm for case 260 c t op operating temperature range -40 to +150 c note 1: for a surge greater than the maximum values, the diode will fail in short-circuit. symbol parameter value unit r th(j-a) junction to ambient on printed circuit on recommended pad layout 220 c/w symbol parameter v rm stand-off voltage v br breakdown voltage v cl clamping voltage i rm leakage current i pp peak pulse current t voltage temperature coefficient v f forward voltage drop c capacitance rd dynamic resistance part number v br @ i r i rm @ v rm r d tc min. max. max. typ. max. typ. @ 0v vv ma a v m ? 10 -4 /c pf ESDA6V1P6 6.1 7.2 1 0.5 3 610 4 50 v i v cl v br v rm i f v f i rm i pp slope: 1/r d
ESDA6V1P6 3/8 ? fig. 1: peak power dissipation versus initial junction temperature. fig. 2: peak pulse power versus exponential pulse duration (tj initial = 25c). fig. 3: clamping voltage versus peak pulse current (tj initial = 25c). rectangular waveform tp = 2.5s. fig. 4: peak forward voltage drop versus peak forward current (typical values). fig. 5: capacitance versus reverse applied voltage (typical values). fig. 6: relative variation of leakage current versus junction temperature (typical values). p [t initial] / [t initial=25c] pp j j p pp 0 25 50 75 100 125 150 175 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 t initial (c) j 10 100 1000 1 10 100 t (s) p p (w) pp t initial = 25c j 0 5 10 15 20 25 30 35 40 0.1 1.0 10.0 50.0 v (v) cl i (a) pp tp = 2.5s i (a) fm 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1e-3 1e-2 1e-1 1e+0 v (v) fm t = 25c j 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 20 30 40 50 v (v) r c(pf) f=1mhz v =30mv t =25c osc rms j 25 50 75 100 125 1 10 50 t (c) j i [t ] / i [t =25c] rj rj
ESDA6V1P6 4/8 ? technical information 1. esd protection by ESDA6V1P6 with the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. electrostatic discharge (esd) is a major cause of failure in electronic systems. as a transient voltage suppressor, ESDA6V1P6 is an ideal choice for esd protection by suppressing esd events. it is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDA6V1P6. ESDA6V1P6 serves as a parallel protection elements, connected between the signal line and ground. as the transient rises above the operating voltage of the device, the ESDA6V1P6 becomes a low impedance path diverting the transient current to ground. the clamping voltage is given by the following formula: v cl = v br + r d .i pp as shown in figure a2 , the esd strikes are clamped by the transient voltage suppressor. fig. a2: esd clamping behavior. to have a good approximation of the remaining voltages at both vi/o side, we provide the typical dynamical resistance value r d . by taking into account the following hypothesis: we have: the results of the calculation done v g = 8kv, r g = 330 ? (iec61000-4-2 standard), v br = 6.4v (typ.) and r d = 1.5 ? (typ.) give: this confirms the very low remaining voltage across the device to be protected. it is also important to note that in this approximation the parasitic inductance effect was not taken into account. this could be a few tenths of volts during a few ns at the vi/o side. r d r g v g v br v(i/o) device to be protected esd surge esd6v1p6 i pp r load r g r d ""and""r load r d > > vi o ? () v br r d + v g r g ------- - = vi o ? () 42.8 volts = fig. a: application example. connector ic to be protected i/o2 i/o1 i/o4 i/o3
ESDA6V1P6 5/8 ? 2. crosstalk behavior fig. a3: esd test board. fig. a4: esd test condition. fig. a5: remaining voltage during esd surge. fig. a6: crosstalk phenomenon. 15kv esd air discharge v(i/o) gnd i/o1, i/o2, i/o3 or i/o4 v(i/o) 15kv esd air discharge a: response in the positive way b: response in the negative way r l1 r l2 1g1 12g2 v+ v 2g2 21g1 v+ v line 1 line 2 v g1 v g2 drivers receivers r g1 r g2
ESDA6V1P6 6/8 ? the crosstalk phenomena are due to the coupling between 2 lines. coupling factors ( 12 or 21 ) increase when the gap across lines decreases, particularly in silicon dice. in the ex ample above, the expected signal on load r l2 is 2 v g2 , in fact the real voltage at this point has got an extra value 21 v g2 . this part of the v g1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. this phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals. the perturbed line will be more affected if it works with low voltage signal or high load impedance (few k ? ). 3. pcb layout recommendations as esd is a fast event, the di/dt caused by this surge is about 30a/ns (risetime=1ns, ipeak=30a), that means each nh causes an overvoltage of 30v. thus, the circuit board layout is a critical design step in the suppression of esd induced transients by reducing parasitic inductances. to ensure that, the following guidelines are recommended : the ESDA6V1P6 should be placed as close as possible to the input terminals or connectors. the path length between the esd suppressor and the protected line should be minimized. all conductive loops, including power and ground loops should be minimized. the esd transient return path to ground should be kept as short as possible. the connections from the ground pins to the ground plane should be the shortest possible. fig. a7: analog crosstalk test configuration. fig. a8: typical analog crosstalk response. fig. a9: digital crosstalk test configuration. fig. a10: typical digital crosstalk response. v g gnd i/o1 i/o4 unloaded 50 ? 50 ? port 1 port 2 100.0k 1.0m 10.0m 100.0m 1.0g -100.00 -90.00 -80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00 db f/hz gnd i/o4 i/o1 v g1 21 g1 v unloaded unloaded pulse generator f= 100khz t = 20ns r 0 - 5v crosstalk 21 g1 v
ESDA6V1P6 7/8 ? 4. comparison with varistors low leakage current for transil? device improve the autonomy of portable equipments as mobile better efficiency in terms of esd protection by using transil? device varistors are bidirectional devices and so are not suitable to protect sensitive ics, because they will be submitted to high voltages in the negative way. ratio v cl /v br lower for transil? device less dispersion in terms of v br no ageing phenomena regarding esd events with transil? device higher efficiency in terms of esd protection order code ordering information revision history varistors transil? leakage current -- +++ protection efficiency -- ++ ageing -- ++ part number marking package weight base qty delivery mode ESDA6V1P6 b sot-666ip 2.9 mg 3000 tape & reel table 1: revision history date revision description of changes january-2004 1 first issue 25-may-2004 2 sot-666 internal pad version package change esda 6v1 p6 esd array v min br package: sot-666ip
ESDA6V1P6 8/8 ? package mechanical data sot-666ip (internal pad) foot print dimensions (in millimeters) a3 a (4x) b1 l1 l3 b e1 e l4 l2 d e e1 0.36 0.20 0.30 1.26 2. 30 0.62 0.84 0.20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com ref. dimensions millimeters inches min. max. min. max. a 0.53 0.60 0.021 0.024 a3 0.13 0.18 0.005 0.007 d 1.50 1.70 0.059 0.067 d2 1.05 1.25 0.041 0.049 e 1.50 1.70 0.059 0.067 e1 1.10 1.30 0.043 0.051 e2 0.23 0.43 0.009 0.017 l1 0.11 0.26 0.004 0.010 l2 0.10 0.30 0.004 0.012 l3 0.05 - 0.002 - l4 0.83 ref 0.032 b 0.14 0.25 0.006 0.010 b1 - 0.34 0.013 e 0.50 bsc 0.020 e1 0.20 - 0.008 8 12 8 12
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